1. Field of the Invention
The present invention relates to a memory device and a method of production and method of use of the same and to a semiconductor device and a method of production of the same, more particularly relates to a memory device able to be formed by stacking fine patterns of memory cells etc. with a low alignment precision and a method of production and method of use of the same and to a semiconductor device able to be formed by stacking fine patterns etc. with a low alignment precision, and a method of production of the same.
2. Description of the Related Art
As memory devices, mask read only memories (ROMs), programmable read only memories (PROMs), static random access memories (SRAMs), dynamic random accessor memories (DRAM), flash memories, ferroelectric random access memories (FeRAMs), magnetic random access memories (MRAM), phase change memories, and numerous other solid state memory devices have been developed and produced.
Almost all of the above types of solid state memory devices are prepared using the microprocessing technology referred to as “photolithography” and have memory cell structures using metal-oxide-semiconductor field effect transistors (MOS field effect transistors, hereinafter, also simply referred to as “MOS transistors”).
In all of the above types of memories of the above types of memory devices, microprocessing technology for further reducing the minimum processing line width in photolithography for achieving higher recording densities and lower prices is being developed. Along with this, MOS transistors designed for such microprocessing technology and further memory cell structures, cell recording materials, etc. compatible with them are being developed.
For the microprocessing, processes involving a minimum processing line width F (design rule or node) of 0.13 μm are currently being used for mass production in the cutting edge of the art. The road map is being laid out for this to be reduced to 0.10 μm in the next generation and further 0.07 μm, 0.05 μm, and 0.035 μm in later generations.
If the minimum processing line width is reduced in this way, the size of the memory cells will be reduced according, so the recording density will be improved and memories will be made larger in capacity.
In the currently used photolithography, a light source of the wavelength range referred to as “deep ultraviolet”, that is, a KrF laser having a wavelength of 248 nm, is being used as an exposure light source. Further, in cutting edge processes, an ArF laser having a wavelength of 193 nm is being used. Microprocessing up to 0.10 μm is possible by these.
Further, for future generations, photolithography using extreme ultraviolet rays having a wavelength of 13 nm (EUV) and electron projection lithography (EPL) are considered promising.
However, the types of photolithography using the above light sources are all more expensive than conventional types of photolithography in the light sources, electron beam sources, lens systems, masks, etc. Further, ultra-high precision is required in the mechanical systems since it is necessary to further improve the overlay precision of the masks, that is, the alignment precision. Therefore, even if the microprocessing line width becomes smaller and the recording density of a memory is improved, there is a large problem in the point of the increase in the cost due to the capital costs or the reduction in the throughput.
The alignment precision is for example about 30% of the minimum processing line width. If the minimum processing line width is 0.05 μm, a precision of 0.015 μm will be necessary.
As a technology enabling microprocessing at a lower cost than the above EUV and EPL, low energy electron projection lithography (LEEPL) has been known.
“LEEPL” is a method using a thin mask having openings of equal magnification and the same shapes as the processed shapes and passing low energy electrons through the openings to strike and thereby expose a resist covering the surface of the processed material.
On the other hand, as an inexpensive microprocessing technology different from the above photolithography, for example, Y. Xia and G. M. Whitesides, “Soft Lithography”, Angew. Chem. Int. Ed., 37 (1998), pp. 550–575 discloses the technology referred to as “soft lithography”.
In soft lithography, microprocessing is performed by bringing an elastic body formed in advance on its surface with fine relief patterns into contact with for example a resist on the surface of the substrate to be micropatterned to transfer the relief pattern of the elastic body to the resist on the substrate and forming them on the substrate by subsequent etching or other processes.
The above elastic body is formed by a plastic, a thin inorganic material, or the like. Since a soft material is used, the above lithography technology is referred to as “soft lithography”.
Also, W. Hinsberg, F. A. Houle, J. Hoffnagle, M. Sanchez, G. Wallraff, M. Morrison, and S. Frank, “Deep-ultraviolet interferometric lithography as a tool for assessment of chemically amplified photoresist performance”, J. Vac. Sci. Technol. B, 16, pg. 3689 (1998) discloses the inexpensive lithography method referred to as “interference exposure”.
In interference exposure, a phase-aligned laser beam is split into two in space by a beam splitter, the two split beams are made to strike the resist on the surface of the substrate for patterning from different directions, and the two beams are made to interfere with each other on the resist surface so as to form a line pattern having a fine period on the resist surface.
Further, it is known that the microprocessing line width can be easily reduced not only by photolithography by the conventional reduction projection exposure systems referred to as “steppers” or “scanners”, but also by so-called contact exposure bringing a mask into direct contact with the resist on the surface of the substrate to be patterned.
In this case, ultraviolet (UV) light or an electron beam is used as the source.
Further, as technologies contributing to improvement of the recording density and lower costs other than the above microprocessing technologies, multi-value storage or multi-bit storage in a single memory cell is being developed.
For example, in a flash memory, data is recorded by storing a charge in a floating gate directly above a gate oxide film of a MOS transistor. Here, for improving the recording density, technology is known for improving the recording density by so-called multi-value storage storing 2 bits of data in a single cell by for example not setting the stored charge to the conventional two levels, but setting it to for example four levels.
Further, in a memory referred to as a “MONOS”, data is recorded by arranging a silicon nitride film directly above the gate oxide film of a MOS transistor and storing a charge at its defect level. Here, technology is known for improving the effective recording density by so-called multi-bit storage storing a bit for storing a charge in the portion of the nitride film in proximity to the source portion of the MOS transistor and a bit for storing it in the portion of the nitride film in proximity to the drain portion.
In the above flash memory or MONOS or other charge storage type memory, it is possible to improve the recording density by the technique of multi-value or multi-bit storage in addition to microprocessing, but it is known that the charge stored in a portion isolated by an insulating film falls due to leakage along with the elapse of time, so there is a problem in the reliability of data retention.
In the future, the stored charge will decrease along with advances in microprocessing, so this will be a difficult to avoid problem.
Furthermore, as technology contributing to the improvement of the recording density and the lower costs, stacking of multiple cell layers is being developed.
In a flash memory or MONOS or other charge storage type memory, the change in the gate threshold voltage of a MOS transistor in accordance with the storage of a charge is used for reproduction, so a MOS transistor is required for the memory cell. A MOS transistor requires a silicon single crystal for forming a channel portion and a high grade thin insulating film at the gate portion, so is formed on a silicon substrate surface. Therefore, it is difficult to stack MOS transistors having similar performances.
Accordingly, in a memory using MOS transistors for the cells, fabrication of a so-called multi-layer memory or three-dimensional memory stacking memory cells is difficult.
On the other hand, as a multi-layer memory or three-dimensional memory, for example, a PROM using memory cells configured by providing anti-fuse recording materials and diodes serially connected with the same such as pn diodes, metal-insulator-metal (MIM) diodes, and Schottky diodes at intersecting positions of two interconnect patterns extending in two directions is disclosed in U.S. Pat. No. 6,034,882.
In the above PROM, interconnects and cells are alternately stacked on the substrate in a direction vertical to the substrate to construct a multi-layer memory or three-dimensional memory. In this case, since MOS transistors are used for the cells, it is possible to stack the cells relatively easily, but keeping down the threshold voltage of the diodes and further keeping down variations in the same to achieve uniform characteristics becomes a problem.
For example, in a silicon pn junction diode, the threshold voltage is about 0.6V, so with each succeeding generation of microprocessing in the future, there will be the problem of the threshold voltage of the diodes becomes the same degree as or higher than the operating voltage of the MOS transistors used in peripheral circuits or the device power supply voltage.
Further, for a MIM diode, the phenomenon of electrons tunneling through the insulating film, that is, the so-called “tunnel effect”, is used, so the film thickness required for low voltage driving becomes an extremely thin one of several nm. It is necessary to control the thickness with a very high precision. This becomes a problem in practice.
Further, a Schottky diode uses the interface phenomenon between a metal and the surface of a semiconductor. It is necessary to control the state of the interface to an extremely high quality. Therefore, this is not suitable for a stacked structure like that of a multi-layer memory.
Further, in the above pn junction diode or Schottky diode, the diode is formed by forming a depletion layer between different types of materials, but a distance of about 100 nm is required for a pn junction diode and a distance of tens of nm or more is required in a Schottky diode for the formation of the depletion layer.
When the size of the microprocessing becomes 100 nm or less, if the thickness of only the diode becomes tens of nm or more, since the recording material is further connected to this in series, the aspect ratio of processing becomes 1 or more or 2 or more, so the problem of a drop in the yield of the microprocessing is also feared.
A PROM using a fuse or anti-fuse or the like as a recording material has a simpler structure in comparison with a RAM capable of repeated recording and can be fabricated by a simple process, so is a recording device perfect for reduction of the bit unit cost, but can only record once, so imposes a large constraint on the specifications and applications.
Summarizing the problems to be solved by the invention, the microprocessing technology required for lowering the cost per bit of a memory device is high in capital cost in both the case of EUV and EPL. In other microprocessing methods including the microprocessing technology LEEPL, there is the problem that it is difficult to secure the alignment precision required in accordance with the minimum processing line width.
Further, the above soft lithography, interference exposure, contact exposure, and other methods known as inexpensive microprocessing technology are suitable for processing fine line widths, but are not capable of precision alignment.